A spin-on-glass (SOG) film modification technology, using a fluoroalkoxysilane [FSi(OR)3] vapor treatment (FAST) at room temperature, is developed. The silanol-based SOG films with the thickness of about 0.25 μm can be modified by the fluorotriethoxysilane (FTES) monomers, and their properties are improved with increasing the FAST time. It has been revealed that the fluorine atoms are deeply and uniformly distributed across the modified SOG films. It has also been clarified that the modified SOG films have tightly bonded Si-O networks with less residual OH radical than those without the FAST process. At the FAST time of 120 min, the modified SOG film's refractive index is 1.398, density is 2.20 g/cm3, and shrinkage is -5% (increase). The hypothetical mechanism of the FAST is: fluoroalkoxysilane monomers are diffused into the SOG films, adsorbed to the Si-OH bonds existing in the SOG precursors, then the precursors are cross-linked with assistance of FTES monomers by a catalytic dehydration reaction at room temperature. Warpage variations for a 500 μm thick, 4 in. Si wafer with a 0.25 μm thick modified SOG film in a heating cycle with the temperatures ranging from 25 to 430°C are less than 2.1 μm which is three times smaller than those without the FAST process (6,3 μm). The moisture absorbed in the modified SOG films is about 2 weight percent (w/o) which is eight times smaller than that without the FAST process (16 w/o). The leakage current through the films, measured using an Al/SOG film/p-Si structure (-5 V to Al) decreases with increasing the FAST time. The leakage current at the FAST time of 120 min is about three orders of magnitude smaller than those without the FAST process. The FAST technique has been applied to interlayer dielectric film planarization of a double level Al interconnection without using any SOG etchback process, where pure Al is used as wiring materials. The surface planarization characteristics are better than those using the conventional SOG etchback process. Neither crack nor void is observed in the trenches between the Al wirings. For the double level Al interconnections formed on 4 in. Si wafers, via hole resistances and yields, which have been obtained from five wafers with 100 chips of 10,000 via chains on each wafer, are 0.11 to 0.13 Ω/unit and 98%, respectively. The via hole diameter in this experiment is 0.9 μm. The via hole resistance increase and open circuit, which are very common in the conventional SOG planarization process without using any SOG etchback, has not been observed for the double level Al interconnections, even without using any SOG etchback process.
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