A study of self-dithering for ΔΣ fractional-N PLL

Yuji Kato, Eri Ioka, Yasuyuki Matsuya

研究成果: Article

抜粋

The ΔΣ fractional-N phase-locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the ΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.

元の言語English
ページ(範囲)9-14
ページ数6
ジャーナルElectronics and Communications in Japan
98
発行部数1
DOI
出版物ステータスPublished - 2015 1 1
外部発表Yes

ASJC Scopus subject areas

  • Signal Processing
  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering
  • Applied Mathematics

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