抄録
The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 234-238 |
| ページ数 | 5 |
| ジャーナル | IEEJ Transactions on Electronics, Information and Systems |
| 巻 | 133 |
| 発行部数 | 2 |
| DOI | |
| 出版物ステータス | Published - 2013 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
A study of self-dithering for ΔΣ fractional-N PLL. / Kato, Yuji; Ioka, Eri; Matsuya, Yasuyuki.
：: IEEJ Transactions on Electronics, Information and Systems, 巻 133, 番号 2, 2013, p. 234-238.研究成果: Article
}
TY - JOUR
T1 - A study of self-dithering for ΔΣ fractional-N PLL
AU - Kato, Yuji
AU - Ioka, Eri
AU - Matsuya, Yasuyuki
PY - 2013
Y1 - 2013
N2 - The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.
AB - The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.
KW - Dithering
KW - Fractional-N
KW - Limit-cycle
KW - PLL
KW - ΔΣ modulator
UR - http://www.scopus.com/inward/record.url?scp=84874168828&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874168828&partnerID=8YFLogxK
U2 - 10.1541/ieejeiss.133.234
DO - 10.1541/ieejeiss.133.234
M3 - Article
AN - SCOPUS:84874168828
VL - 133
SP - 234
EP - 238
JO - IEEJ Transactions on Electronics, Information and Systems
JF - IEEJ Transactions on Electronics, Information and Systems
SN - 0385-4221
IS - 2
ER -