A study of self-dithering for ΔΣ fractional-N PLL

Yuji Kato, Eri Ioka, Yasuyuki Matsuya

研究成果: Article

抜粋

The ΔΣ fractional-N PLL is been researched to realize a low fractional spurious signal characteristic. In this PLL, theΔΣ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the ΔΣ modulator when the input value is fixed. As a result, the limit cycle oscillation increases a spurious signal power. Therefore, some method is required for suppressing this oscillation. In this paper, we propose a self-dithering ΔΣ fractional-N PLL that inhibits the limit cycle oscillation without the external dither generating circuit. The proposed circuit generates the dither from internal signals of PLL. We simulated the output spectrum of the proposed circuit. As a result, we show that the proposed circuit suppressed the limit cycle oscillation, and that the spurious level of the proposed circuit was almost equals to a spurious level without the limit cycle oscillation.

元の言語English
ページ(範囲)234-238
ページ数5
ジャーナルIEEJ Transactions on Electronics, Information and Systems
133
発行部数2
DOI
出版物ステータスPublished - 2013
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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