An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

研究成果: Article査読

1 被引用数 (Scopus)

抄録

In this paper, we first propose an HDR-mcd architecture, which integrates periodically all-in-phase based multiple clock domains and multi-cycle interconnect communication into high-level synthesis. In HDR-mcd, an entire chip is divided into several huddles. Huddles can realize synchronization between different clock domains in which interconnection delay should be considered during high-level synthesis. Next, we propose a high-level synthesis algorithm for HDR-mcd, which can reduce energy consumption by optimizing configuration and placement of huddles. Experimental results show that the proposed method achieves 32.5% energy-saving compared with the existing single clock domain based methods

本文言語English
ページ(範囲)1376-1391
ページ数16
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E98A
7
DOI
出版ステータスPublished - 2015 7 1

ASJC Scopus subject areas

  • 電子工学および電気工学
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 応用数学
  • 信号処理

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