An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

抄録

In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

本文言語English
ホスト出版物のタイトル2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOI
出版ステータスPublished - 2013 8 15
イベント2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan, Province of China
継続期間: 2013 4 222013 4 24

出版物シリーズ

名前2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
国/地域Taiwan, Province of China
CityHsinchu
Period13/4/2213/4/24

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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