Analysis and characterization of PDN impedance and SSO noise of 4k-IO 3D SiP

Hiroki Takatani, Yosuke Tanaka, Haruya Fujita, Yoshiaki Oizono, Yoshitaka Nabeshima, Toshio Sudo, Atsushi Sakai, Shiro Uchiyama, Hiroaki Ikeda

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

The this paper deals with the analysis of power distribution network (PDN) impedance and simultaneous switching output buffer (SSO) noise for a 3D system-in package (SiP) with 4k-IO widebus structure. The 3D SiP consisted of 3 stacked chips (a memory chip on the top, Si interposer in the middle, and a logic chip) and an organic package substrate. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer and the logic chip. The PDN impedance for each chip was extracted by using XcitePI (Sigrity Inc.). Then, the PDN impedance for the organic package substrate was extracted by using SIwave (Ansys Inc.). Finally, the total PDN impedance was synthesized to estimate the power supply disturbance due to the anti-resonance peak.

本文言語English
ホスト出版物のタイトル2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
ページ185-188
ページ数4
DOI
出版ステータスPublished - 2012 12 1
イベント2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei, Taiwan, Province of China
継続期間: 2012 12 92012 12 11

出版物シリーズ

名前2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012

Conference

Conference2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
CountryTaiwan, Province of China
CityTaipei
Period12/12/912/12/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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