Analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

Akira Wakabayashi, Yasutaka Mitani, Kazushige Horio

研究成果: Article

20 引用 (Scopus)

抜粋

Two-dimensional analysis of gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs is performed, and their dependence on the structural parameters and the off-state gate voltage V Goff is studied. It is shown that when V Goff is around the threshold voltage (pinchoff voltage) V th, the gate-lag could be almost eliminated by introducing the buried-gate structure. However, it is suggested that large gate-lag might be seen when V Goff is much more negative than V th.

元の言語English
ページ(範囲)37-41
ページ数5
ジャーナルIEEE Transactions on Electron Devices
49
発行部数1
DOI
出版物ステータスPublished - 2002 1 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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