Analysis of removal of surface-state-related lags and current slump in GaAs FETs

H. Hafiz, Masatoshi Kumeno, Kazushige Horio

研究成果: Article

2 引用 (Scopus)

抄録

Two-dimensional transient analysis of field-plate GaAs MESFETs is performed by considering surface states in the region from the gate toward the drain. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump because of surface states are reduced by introducing a field plate longer than the surface-state region. Dependence of drain lag, gate lag, and current slump on the field-plate length and SiO2 passivation layer thickness is studied, indicating that the lags and current slump can be completely removed in a case with a thin SiO2 layer.

元の言語English
記事番号6603270
ページ(範囲)1361-1363
ページ数3
ジャーナルIEEE Electron Device Letters
34
発行部数11
DOI
出版物ステータスPublished - 2013

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Surface states
Field effect transistors
Passivation
Transient analysis
Electric potential
gallium arsenide

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

これを引用

Analysis of removal of surface-state-related lags and current slump in GaAs FETs. / Hafiz, H.; Kumeno, Masatoshi; Horio, Kazushige.

:: IEEE Electron Device Letters, 巻 34, 番号 11, 6603270, 2013, p. 1361-1363.

研究成果: Article

@article{e4d231db56084ce6b6ceb5a10a937a2f,
title = "Analysis of removal of surface-state-related lags and current slump in GaAs FETs",
abstract = "Two-dimensional transient analysis of field-plate GaAs MESFETs is performed by considering surface states in the region from the gate toward the drain. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump because of surface states are reduced by introducing a field plate longer than the surface-state region. Dependence of drain lag, gate lag, and current slump on the field-plate length and SiO2 passivation layer thickness is studied, indicating that the lags and current slump can be completely removed in a case with a thin SiO2 layer.",
keywords = "2-D analysis, current slump, drain lag, GaAs field effect transistor (FET), gate lag, surface state",
author = "H. Hafiz and Masatoshi Kumeno and Kazushige Horio",
year = "2013",
doi = "10.1109/LED.2013.2279833",
language = "English",
volume = "34",
pages = "1361--1363",
journal = "IEEE Electron Device Letters",
issn = "0741-3106",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - Analysis of removal of surface-state-related lags and current slump in GaAs FETs

AU - Hafiz, H.

AU - Kumeno, Masatoshi

AU - Horio, Kazushige

PY - 2013

Y1 - 2013

N2 - Two-dimensional transient analysis of field-plate GaAs MESFETs is performed by considering surface states in the region from the gate toward the drain. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump because of surface states are reduced by introducing a field plate longer than the surface-state region. Dependence of drain lag, gate lag, and current slump on the field-plate length and SiO2 passivation layer thickness is studied, indicating that the lags and current slump can be completely removed in a case with a thin SiO2 layer.

AB - Two-dimensional transient analysis of field-plate GaAs MESFETs is performed by considering surface states in the region from the gate toward the drain. Quasi-pulsed current-voltage curves are derived from the transient characteristics. It is shown that drain lag and current slump because of surface states are reduced by introducing a field plate longer than the surface-state region. Dependence of drain lag, gate lag, and current slump on the field-plate length and SiO2 passivation layer thickness is studied, indicating that the lags and current slump can be completely removed in a case with a thin SiO2 layer.

KW - 2-D analysis

KW - current slump

KW - drain lag

KW - GaAs field effect transistor (FET)

KW - gate lag

KW - surface state

UR - http://www.scopus.com/inward/record.url?scp=84887234099&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84887234099&partnerID=8YFLogxK

U2 - 10.1109/LED.2013.2279833

DO - 10.1109/LED.2013.2279833

M3 - Article

AN - SCOPUS:84887234099

VL - 34

SP - 1361

EP - 1363

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

IS - 11

M1 - 6603270

ER -