Analysis of surface-state effects on gate-lag phenomena in recessed-gate and buried-gate GaAs MESFETs

K. Horio, A. Wakabayashi, T. Yamada

研究成果: Paper査読

1 被引用数 (Scopus)

抄録

Gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional analysis including surface-state effects. It is shown that in a recessed-gate structure, the gate-lag is reduced to some extent by increasing the recess depth, but it may not be so much suppressed as expected because the surface states around the gate affect the turn-on characteristics. However, by introducing the buried-gate structure where the gate electrode is attached to the vertical planes of the recess and (also) to the same planes as the drain electrode, the surface-state effects are minimized, and the gate-lag can be greatly reduced.

本文言語English
ページ191-194
ページ数4
DOI
出版ステータスPublished - 1999
イベントProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits - Singapore, Singapore
継続期間: 1999 7 51999 7 9

Other

OtherProceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits
CitySingapore, Singapore
Period99/7/599/7/9

ASJC Scopus subject areas

  • 工学(全般)

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