Gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional analysis including surface-state effects. It is shown that in a recessed-gate structure, the gate-lag is reduced to some extent by increasing the recess depth, but it may not be so much suppressed as expected because the surface states around the gate affect the turn-on characteristics. However, by introducing the buried-gate structure where the gate electrode is attached to the vertical planes of the recess and (also) to the same planes as the drain electrode, the surface-state effects are minimized, and the gate-lag can be greatly reduced.
|出版ステータス||Published - 1999|
|イベント||Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits - Singapore, Singapore|
継続期間: 1999 7 5 → 1999 7 9
|Other||Proceedings of the 1999 7th International Symposium on Physical and Failure Analysis of Integrated Circuits|
|Period||99/7/5 → 99/7/9|
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