Analytical expression of quantization noise in time-to-digital converter based on the fourier series analysis

Tadashi Maeda, Takashi Tokairin

研究成果: Article

6 引用 (Scopus)

抜粋

This paper describes a simple, analytical expression for quantization noise in a time-to-digital converter (TDC) based on Fourier-series analysis. We analyzed inverter propagation-delay variations due to fluctuations in the threshold voltage, and here we also discuss phase noise in an all-digital phase locked loop (ADPLL). The large standard deviation in the threshold voltage degrades phase noise even under short inverter-delay conditions. Increasing the gate area of transistors led to low phase noise due to threshold variations, but greatly increased power consumption. The paper also discusses TDC power reduction method without degrading quantization noise. Our analytically predicted results agreed well with the data obtained from a Spectre-RF simulator.

元の言語English
記事番号5371917
ページ(範囲)1538-1548
ページ数11
ジャーナルIEEE Transactions on Circuits and Systems I: Regular Papers
57
発行部数7
DOI
出版物ステータスPublished - 2010 1 6

    フィンガープリント

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用