Anti-resonance peak damping of PDN impedance by on-board snubber circuits

You Iijima, Masataka Matsumura, Toshio Sudo

研究成果: Conference contribution

3 引用 (Scopus)

抄録

Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced CMOS circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.

元の言語English
ホスト出版物のタイトル2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
ページ127-130
ページ数4
DOI
出版物ステータスPublished - 2012
イベント2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 - Taipei
継続期間: 2012 12 92012 12 11

Other

Other2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Taipei
期間12/12/912/12/11

Fingerprint

Damping
Networks (circuits)
Field programmable gate arrays (FPGA)
Signal interference
Electric network analysis
Capacitance

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Iijima, Y., Matsumura, M., & Sudo, T. (2012). Anti-resonance peak damping of PDN impedance by on-board snubber circuits. : 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012 (pp. 127-130). [6469429] https://doi.org/10.1109/EDAPS.2012.6469429

Anti-resonance peak damping of PDN impedance by on-board snubber circuits. / Iijima, You; Matsumura, Masataka; Sudo, Toshio.

2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 127-130 6469429.

研究成果: Conference contribution

Iijima, Y, Matsumura, M & Sudo, T 2012, Anti-resonance peak damping of PDN impedance by on-board snubber circuits. : 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012., 6469429, pp. 127-130, 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012, Taipei, 12/12/9. https://doi.org/10.1109/EDAPS.2012.6469429
Iijima Y, Matsumura M, Sudo T. Anti-resonance peak damping of PDN impedance by on-board snubber circuits. : 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. p. 127-130. 6469429 https://doi.org/10.1109/EDAPS.2012.6469429
Iijima, You ; Matsumura, Masataka ; Sudo, Toshio. / Anti-resonance peak damping of PDN impedance by on-board snubber circuits. 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012. 2012. pp. 127-130
@inproceedings{1bec56bebe034771b3882be5a7a4fe0f,
title = "Anti-resonance peak damping of PDN impedance by on-board snubber circuits",
abstract = "Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced CMOS circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.",
author = "You Iijima and Masataka Matsumura and Toshio Sudo",
year = "2012",
doi = "10.1109/EDAPS.2012.6469429",
language = "English",
isbn = "9781467314435",
pages = "127--130",
booktitle = "2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012",

}

TY - GEN

T1 - Anti-resonance peak damping of PDN impedance by on-board snubber circuits

AU - Iijima, You

AU - Matsumura, Masataka

AU - Sudo, Toshio

PY - 2012

Y1 - 2012

N2 - Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced CMOS circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.

AB - Simultaneous switching noise (SSN) is a serious design issue to stabilize logic operation and to reduce electromagnetic interference (EMI) in advanced CMOS circuits and systems. Ringing frequency observed in the SSN waveforms is strongly related to the anti-resonance peak frequency of total PDN impedance. In this paper, on-board snubber (RC series circuit) was investigated to improve power supply integrity in a FPGA (Field Programmable Gate Array) board. The on-board snubber circuits was added just at the beneath of the power supply terminals of the FPGA to effectively suppress the anti-resonance peak of the total PDN impedance. Design space to damp the anti-resonance peak was examined. In particular, the values of on-board capacitance and resistance of snubber circuit has been examined by using circuit analysis tool and field solver.

UR - http://www.scopus.com/inward/record.url?scp=84875519460&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84875519460&partnerID=8YFLogxK

U2 - 10.1109/EDAPS.2012.6469429

DO - 10.1109/EDAPS.2012.6469429

M3 - Conference contribution

AN - SCOPUS:84875519460

SN - 9781467314435

SP - 127

EP - 130

BT - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012

ER -