Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, Kazutaka Nogami, Mutsunori Igarashi, Fumihiro Minami, Yukio Kawasaki, Takashi Ishikawa, Masahiro Kanazawa, Takahiro Aoki, Midori Takano, Chiharu Mizuno, Makoto Ichida, Shinji Sonoda, Makoto Takahashi, Naoyuki Hatanaka

研究成果: Conference contribution

22 引用 (Scopus)

抜粋

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.

元の言語English
ホスト出版物のタイトルProceedings of the Custom Integrated Circuits Conference
出版者IEEE
ページ131-134
ページ数4
出版物ステータスPublished - 1997
外部発表Yes
イベントProceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
継続期間: 1997 5 51997 5 8

Other

OtherProceedings of the 1997 IEEE Custom Integrated Circuits Conference
Santa Clara, CA, USA
期間97/5/597/5/8

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Usami, K., Nogami, K., Igarashi, M., Minami, F., Kawasaki, Y., Ishikawa, T., ... Hatanaka, N. (1997). Automated low-power technique exploiting multiple supply voltages applied to a media processor. : Proceedings of the Custom Integrated Circuits Conference (pp. 131-134). IEEE.