This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. Combining these techniques together, we applied it to the random logic modules of a media processor chip. The combined technique reduced the power by 47% on average with an area overhead of 15% at the random logic, while keeping the performance.
|ジャーナル||Proceedings of the Custom Integrated Circuits Conference|
|出版ステータス||Published - 1997|
|イベント||Proceedings of the 1997 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA|
継続期間: 1997 5月 5 → 1997 5月 8
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