Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, Mutsunori Igarashi, Fumihiro Minami, Takashi Ishikawa, Masahiro Kanazawa, Makoto Ichida, Kazutaka Nogami

研究成果: Article査読

203 被引用数 (Scopus)

抄録

This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.

本文言語English
ページ(範囲)463-472
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
33
3
DOI
出版ステータスPublished - 1998 3 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

フィンガープリント

「Automated low-power technique exploiting multiple supply voltages applied to a media processor」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル