This paper describes an automated design technique to selectively use multi-threshold CMOS (MTCMOS) in a cell-by-cell fashion. MT cells consisting of low-Vth transistors and high-Vth sleep transistors are assigned to critical paths, while high-Vth cells are assigned to non-critical paths. Compared to the conventional MTCMOS, the gate delay is not affected by the discharge patterns of other gates because there is no virtual ground to be shared. We applied this technique to a test chip of a DSP core. The worst path-delay was improved by 14% over the single high-Vth design without increasing standby leakage at 10% area overhead.
|出版物ステータス||Published - 2002 12 1|
|イベント||Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States|
継続期間: 2002 8 12 → 2002 8 14
|Conference||Proceedings of the 2002 International Symposium on Low Power Electronics and Design|
|期間||02/8/12 → 02/8/14|
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