抄録
Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 1931-1933 |
| ページ数 | 3 |
| ジャーナル | Physica Status Solidi (C) Current Topics in Solid State Physics |
| 巻 | 7 |
| 発行部数 | 7-8 |
| DOI | |
| 出版物ステータス | Published - 2010 |
Fingerprint
ASJC Scopus subject areas
- Condensed Matter Physics
これを引用
Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs. / Horio, Kazushige; Nakajima, Atsushi.
：: Physica Status Solidi (C) Current Topics in Solid State Physics, 巻 7, 番号 7-8, 2010, p. 1931-1933.研究成果: Article
}
TY - JOUR
T1 - Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs
AU - Horio, Kazushige
AU - Nakajima, Atsushi
PY - 2010
Y1 - 2010
N2 - Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.
AB - Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.
KW - AlGaN/GaN
KW - Design
KW - HEMTs
KW - Simulation
KW - Surface states
KW - Trap levels
UR - http://www.scopus.com/inward/record.url?scp=77955789534&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955789534&partnerID=8YFLogxK
U2 - 10.1002/pssc.200983418
DO - 10.1002/pssc.200983418
M3 - Article
AN - SCOPUS:77955789534
VL - 7
SP - 1931
EP - 1933
JO - Physica Status Solidi (C) Current Topics in Solid State Physics
JF - Physica Status Solidi (C) Current Topics in Solid State Physics
SN - 1862-6351
IS - 7-8
ER -