Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs

Kazushige Horio, Atsushi Nakajima

研究成果: Article

2 引用 (Scopus)

抄録

Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.

元の言語English
ページ(範囲)1931-1933
ページ数3
ジャーナルPhysica Status Solidi (C) Current Topics in Solid State Physics
7
発行部数7-8
DOI
出版物ステータスPublished - 2010

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high electron mobility transistors
time lag
buffers
traps
electrons
electric potential
simulation

ASJC Scopus subject areas

  • Condensed Matter Physics

これを引用

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AU - Horio, Kazushige

AU - Nakajima, Atsushi

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N2 - Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.

AB - Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.

KW - AlGaN/GaN

KW - Design

KW - HEMTs

KW - Simulation

KW - Surface states

KW - Trap levels

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