Buffer-trap and surface-state effects on gate lag in AlGaN/GaN HEMTs

Kazushige Horio, Atsushi Nakajima

研究成果: Conference article査読

5 被引用数 (Scopus)

抄録

Two-dimensional simulation of turn-on characteristics of Al-GaN/GaN HEMTs is performed in which both buffer traps and surface states are considered. It is studied how the so-called gate lag is affected by these factors. It is shown that gate lag due to buffer traps can occur because in the off state where the gate voltage is negative, electrons are injected into the buffer layer and captured by the traps, leading to more negatively charged buffer layer. It is also shown that gate lag due to an electron-trap-type surface state can occur only when electron's gate tunneling is considered.

本文言語English
ページ(範囲)1931-1933
ページ数3
ジャーナルPhysica Status Solidi (C) Current Topics in Solid State Physics
7
7-8
DOI
出版ステータスPublished - 2010 8 26
イベント8th International Conference on Nitride Semiconductors, ICNS-8 - Jeju, Korea, Republic of
継続期間: 2009 10 182009 10 23

ASJC Scopus subject areas

  • 凝縮系物理学

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