TY - JOUR
T1 - Buffer-trapping effects on drain lag and power compression in GaN FET
AU - Horio, K.
AU - Yonemoto, K.
PY - 2005
Y1 - 2005
N2 - Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when VD is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.
AB - Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when VD is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.
UR - http://www.scopus.com/inward/record.url?scp=27344434560&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=27344434560&partnerID=8YFLogxK
U2 - 10.1002/pssc.200461311
DO - 10.1002/pssc.200461311
M3 - Article
AN - SCOPUS:27344434560
VL - 2
SP - 2635
EP - 2638
JO - Physica Status Solidi C: Conferences
JF - Physica Status Solidi C: Conferences
SN - 1610-1634
IS - 7
ER -