Chip-package co-design for suppressing parallel resonance and power supply noise

Tatsuya Mido, Ryota Kobayashi, Genki Kubo, Hiroki Otsuka, Yoshinori Kobayashi, Hideyuki Fujii, Toshio Sudo

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.

本文言語English
ホスト出版物のタイトル2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
ページ347-350
ページ数4
DOI
出版ステータスPublished - 2012 12 1
イベント2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012 - Tempe, AZ, United States
継続期間: 2012 10 212012 10 24

出版物シリーズ

名前2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012

Conference

Conference2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
国/地域United States
CityTempe, AZ
Period12/10/2112/10/24

ASJC Scopus subject areas

  • 電子工学および電気工学

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