TY - GEN
T1 - Chip-package co-design for suppressing parallel resonance and power supply noise
AU - Mido, Tatsuya
AU - Kobayashi, Ryota
AU - Kubo, Genki
AU - Otsuka, Hiroki
AU - Kobayashi, Yoshinori
AU - Fujii, Hideyuki
AU - Sudo, Toshio
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
AB - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
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U2 - 10.1109/EPEPS.2012.6457913
DO - 10.1109/EPEPS.2012.6457913
M3 - Conference contribution
AN - SCOPUS:84874489787
SN - 9781467325394
T3 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
SP - 347
EP - 350
BT - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
T2 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Y2 - 21 October 2012 through 24 October 2012
ER -