Clustered voltage scaling technique for low-power design

Kimiyoshi Usami, Mark Horowitz

研究成果: Conference contribution

322 引用 (Scopus)

抄録

This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

元の言語English
ホスト出版物のタイトルProceedings of the International Symposium on Low Power Design
出版場所New York, NY, United States
出版者ACM
ページ3-8
ページ数6
出版物ステータスPublished - 1995
外部発表Yes
イベントProceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA
継続期間: 1995 4 231995 4 26

Other

OtherProceedings of the 1995 International Symposium on Low Power Design
Dana Point, CA, USA
期間95/4/2395/4/26

Fingerprint

Networks (circuits)
Electric potential
Microprocessor chips
Voltage scaling

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Usami, K., & Horowitz, M. (1995). Clustered voltage scaling technique for low-power design. : Proceedings of the International Symposium on Low Power Design (pp. 3-8). New York, NY, United States: ACM.

Clustered voltage scaling technique for low-power design. / Usami, Kimiyoshi; Horowitz, Mark.

Proceedings of the International Symposium on Low Power Design. New York, NY, United States : ACM, 1995. p. 3-8.

研究成果: Conference contribution

Usami, K & Horowitz, M 1995, Clustered voltage scaling technique for low-power design. : Proceedings of the International Symposium on Low Power Design. ACM, New York, NY, United States, pp. 3-8, Proceedings of the 1995 International Symposium on Low Power Design, Dana Point, CA, USA, 95/4/23.
Usami K, Horowitz M. Clustered voltage scaling technique for low-power design. : Proceedings of the International Symposium on Low Power Design. New York, NY, United States: ACM. 1995. p. 3-8
Usami, Kimiyoshi ; Horowitz, Mark. / Clustered voltage scaling technique for low-power design. Proceedings of the International Symposium on Low Power Design. New York, NY, United States : ACM, 1995. pp. 3-8
@inproceedings{77586ea12e3c4a159aa7e2ffdc988771,
title = "Clustered voltage scaling technique for low-power design",
abstract = "This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20{\%}.",
author = "Kimiyoshi Usami and Mark Horowitz",
year = "1995",
language = "English",
pages = "3--8",
booktitle = "Proceedings of the International Symposium on Low Power Design",
publisher = "ACM",

}

TY - GEN

T1 - Clustered voltage scaling technique for low-power design

AU - Usami, Kimiyoshi

AU - Horowitz, Mark

PY - 1995

Y1 - 1995

N2 - This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

AB - This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

UR - http://www.scopus.com/inward/record.url?scp=0029193696&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0029193696&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0029193696

SP - 3

EP - 8

BT - Proceedings of the International Symposium on Low Power Design

PB - ACM

CY - New York, NY, United States

ER -