Clustered voltage scaling technique for low-power design

Kimiyoshi Usami, Mark Horowitz

研究成果: Paper査読

325 被引用数 (Scopus)

抄録

This paper describes a technique to reduce power without changing circuit performance by making use of two supply voltages. Gates off the critical path are run at the lower supply to reduce power. To minimize the number of interfacing level-converters needed, our algorithm clusters the circuits which operate at reduced voltage, leading to clustered voltage scaling (CVS). We applied the CVS technique to design examples of control logic in a real microprocessor, which had been implemented using a low-power library. Minimizing the power is achieved by combining the gate re-sizing and the CVS technique. The CVS technique was able to further reduce the power by 10-20%.

本文言語English
ページ3-8
ページ数6
DOI
出版ステータスPublished - 1995
外部発表はい
イベントProceedings of the 1995 International Symposium on Low Power Design - Dana Point, CA, USA
継続期間: 1995 4 231995 4 26

Other

OtherProceedings of the 1995 International Symposium on Low Power Design
CityDana Point, CA, USA
Period95/4/2395/4/26

ASJC Scopus subject areas

  • Engineering(all)

フィンガープリント 「Clustered voltage scaling technique for low-power design」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル