CML GAAS 4KB SRAM.

Kazukio Takahashi, Tadashi Maeda, Fumiaki Katano, Takashi Furutsuka, Asamitsu Higashisaka

研究成果: Conference article査読

5 被引用数 (Scopus)

抄録

Summary form only given. A CML-compatible GaAs 4-Kb static RAM has been designed. Source-coupled FET logic was used for the peripheral circuit, because it is suitable for the adjustment of the supply voltages and the input/output levels to the CML level, as well as being able to drive large loads. The memory cell, on the other hand, is composed of conventional E/D-DCFL circuitry. The SRAM was fabricated by using sidewall-assisted closely-spaced-electrode FET technology, where the spacings between source and gate, drain and gate are extremely narrow, to reduce the parasitic series resistances. Separation is by 0. 25- mu m films prepared on both sides of the gate electrode. The device was tested by using both the memory tester and the 50- OMEGA high-speed measurement system and was operable at the CML supply voltage level. Read/write operation was confirmed. The minimum address access time was 2. 4 ns for a power dissipation of 1. 08 W.

本文言語English
ページ(範囲)68-69, 308
ジャーナルDigest of Technical Papers - IEEE International Solid-State Circuits Conference
出版ステータスPublished - 1985 12 1
外部発表はい

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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