Summary form only given. A CML-compatible GaAs 4-Kb static RAM has been designed. Source-coupled FET logic was used for the peripheral circuit, because it is suitable for the adjustment of the supply voltages and the input/output levels to the CML level, as well as being able to drive large loads. The memory cell, on the other hand, is composed of conventional E/D-DCFL circuitry. The SRAM was fabricated by using sidewall-assisted closely-spaced-electrode FET technology, where the spacings between source and gate, drain and gate are extremely narrow, to reduce the parasitic series resistances. Separation is by 0. 25- mu m films prepared on both sides of the gate electrode. The device was tested by using both the memory tester and the 50- OMEGA high-speed measurement system and was operable at the CML supply voltage level. Read/write operation was confirmed. The minimum address access time was 2. 4 ns for a power dissipation of 1. 08 W.
|ジャーナル||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|出版ステータス||Published - 1985 12月 1|
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