抄録
A new computable ordering of digital networks is proposed. The method is particularly efficient when a network is implemented on a signal processor (SP). The algorithm is based on the depth-first search and the optimal code generation algorithm for binary trees. A new high-level language for describing digital networks is also proposed. A program written in the language is compiled using the proposed ordering algorithm to generate an efficient assembler program for an SP.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 1403-1406 |
| ページ数 | 4 |
| ジャーナル | Proceedings - IEEE International Symposium on Circuits and Systems |
| 出版ステータス | Published - 1985 12月 1 |
ASJC Scopus subject areas
- 電子工学および電気工学