Physical mechanism of gate-lag or slow current transient in GaAs MESFETs is studied by two-dimensional simulation including surface-state effects. It is shown that the gate-lag becomes noticeable when the deep-acceptor-like surface state acts as a hole trap. To reduce it, the deep acceptor should be made electron-trap-like, which could be realized by reducing the surface-state density. Structures expected to have less gate-lag, such as a self-aligned structure and a recessed-gate structure are also analyzed. It is physically discussed whether the gate-lag can be completely eliminated in these structures.
|出版ステータス||Published - 1998 12月 1|
|イベント||Proceedings of the 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE'98 - Pisa, Italy|
継続期間: 1998 9月 29 → 1998 10月 2
|Other||Proceedings of the 1998 URSI International Symposium on Signals, Systems, and Electronics, ISSSE'98|
|Period||98/9/29 → 98/10/2|
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