Degradation of electromigration lifetime of Cu/Low-k interconnects by postannealing

Yumi Kakuhara, Kazuyoshi Ueno

研究成果: Article

1 引用 (Scopus)

抄録

The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and itseffect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 °C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.

元の言語English
記事番号046507
ジャーナルJapanese Journal of Applied Physics
48
発行部数4
DOI
出版物ステータスPublished - 2009 4

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Electromigration
electromigration
degradation
Degradation
budgets
life (durability)
Dielectric films
failure modes
Failure modes
voids
interlayers
wafers
Annealing
Fabrication
fabrication
annealing
Temperature
temperature
Hot Temperature

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

これを引用

@article{a622739c631d4322b479112048b276d7,
title = "Degradation of electromigration lifetime of Cu/Low-k interconnects by postannealing",
abstract = "The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and itseffect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 °C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.",
author = "Yumi Kakuhara and Kazuyoshi Ueno",
year = "2009",
month = "4",
doi = "10.1143/JJAP.48.046507",
language = "English",
volume = "48",
journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",
issn = "0021-4922",
publisher = "Japan Society of Applied Physics",
number = "4",

}

TY - JOUR

T1 - Degradation of electromigration lifetime of Cu/Low-k interconnects by postannealing

AU - Kakuhara, Yumi

AU - Ueno, Kazuyoshi

PY - 2009/4

Y1 - 2009/4

N2 - The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and itseffect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 °C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.

AB - The total thermal budget of the wafer fabrication process for structures with multilevel Cu/low-k interconnects has been increasing, and itseffect on the electromigration (EM) reliability of the lower-level interconnects has become a concern. The annealing of packaged samples including two-level interconnects for EM tests was shown here to be an effective method of evaluating the effect of the thermal budget on interconnects. EM lifetime was reduced by postannealing at the maximum process temperature (350 °C), and its failure mode was a slitlike void generated at the interface between the via and the Cu line. It was shown that the degradation mechanism was related to the contact between the via and the Cu line and that postannealing may affect the stress at this contact by changing the stress in the dielectric interlayer film.

UR - http://www.scopus.com/inward/record.url?scp=67849124226&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67849124226&partnerID=8YFLogxK

U2 - 10.1143/JJAP.48.046507

DO - 10.1143/JJAP.48.046507

M3 - Article

AN - SCOPUS:67849124226

VL - 48

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4

M1 - 046507

ER -