Delay modeling and static timing analysis for MTCMOS circuits

Naoaki Ohkubo, Kimiyoshi Usami

研究成果: Conference contribution

5 引用 (Scopus)

抜粋

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

元の言語English
ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ570-575
ページ数6
2006
出版物ステータスPublished - 2006
イベントASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama
継続期間: 2006 1 242006 1 27

Other

OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Yokohama
期間06/1/2406/1/27

    フィンガープリント

ASJC Scopus subject areas

  • Engineering(all)

これを引用

Ohkubo, N., & Usami, K. (2006). Delay modeling and static timing analysis for MTCMOS circuits. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (巻 2006, pp. 570-575). [1594746]