Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

研究成果: Conference contribution

9 被引用数 (Scopus)

抄録

This paper presents a design and control scheme of a microprocessor whose internal function units are power gated at instruction-by-instruction basis. Enabling/disabling the power gating is adaptively controlled under the support of on-chip leakage monitors and the operating system to minimize energy overhead due to sleep-in and wakeup. Measured results of the fabricated chip in the 65nm CMOS technology demonstrated that our approach reduces energy to 21-35% in the range of 25-85°C as compared to the non power-gated case. Energy dissipation was reduced by up to 15% as compared to the conventional fine-grain power gating technique in the same temperature range.

本文言語English
ホスト出版物のタイトル2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings
ページ843-848
ページ数6
DOI
出版ステータスPublished - 2014
イベント2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Suntec, Singapore
継続期間: 2014 1 202014 1 23

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014
国/地域Singapore
CitySuntec
Period14/1/2014/1/23

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学

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