Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yusuke Yoshida, Kimiyoshi Usami

研究成果: Conference contribution

1 引用 (Scopus)

抄録

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

元の言語English
ホスト出版物のタイトルJoint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings
出版者Institute of Electrical and Electronics Engineers Inc.
ページ43-46
ページ数4
ISBN(電子版)9781509053131
DOI
出版物ステータスPublished - 2017 6 29
イベント2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Athens, Greece
継続期間: 2017 4 32017 4 5

Other

Other2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017
Greece
Athens
期間17/4/317/4/5

Fingerprint

Silicon
methodology
Data storage equipment
silicon
cells
energy
latches
Computer peripheral equipment
Flip flop circuits
electric potential
Bias voltage
clocks
Clocks
Energy dissipation
leakage
energy dissipation
Networks (circuits)
Electric potential
simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

これを引用

Yoshida, Y., & Usami, K. (2017). Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. : Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings (pp. 43-46). [7962596] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ULIS.2017.7962596

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. / Yoshida, Yusuke; Usami, Kimiyoshi.

Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 43-46 7962596.

研究成果: Conference contribution

Yoshida, Y & Usami, K 2017, Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. : Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings., 7962596, Institute of Electrical and Electronics Engineers Inc., pp. 43-46, 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017, Athens, Greece, 17/4/3. https://doi.org/10.1109/ULIS.2017.7962596
Yoshida Y, Usami K. Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. : Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 43-46. 7962596 https://doi.org/10.1109/ULIS.2017.7962596
Yoshida, Yusuke ; Usami, Kimiyoshi. / Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX. Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 43-46
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