Design and implementation of fine-grain power gating with ground bounce suppression

Kimiyoshi Usami, Toshiaki Shirai, Tasunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura

研究成果: Conference contribution

25 引用 (Scopus)

抄録

This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement makes suppression of the ground-bounce more difficult. We propose a novel technique to skew the wakeup timings of fine-grain local power domains to suppress the ground bounce. Delay of buffers driving power switches is skewed in the buffer tree by selectively downsizing them. We designed a MIPS R3000 based CPU core in a 90nm CMOS technology and applied our technique to internal function units. Simulation results showed that our technique reduces the rush current to 47% over the case to turn-on the power switches simultaneously. This resulted in suppressing the ground bounce to 53mV with 3.3ns wakeup time. Simulation results from running benchmark programs showed that the total power dissipation for the function units was reduced by up to 15% at 25°C and by 62% at 100°C. Effectiveness in power savings is discussed from the viewpoint of the temperature-dependent break-even points and the consecutive idle time in the program.

元の言語English
ホスト出版物のタイトルProceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
ページ381-386
ページ数6
DOI
出版物ステータスPublished - 2009
イベント22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems - New Delhi
継続期間: 2009 1 52009 1 9

Other

Other22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems
New Delhi
期間09/1/509/1/9

Fingerprint

Switches
Program processors
Energy dissipation
Temperature
Sleep

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

これを引用

Usami, K., Shirai, T., Hashida, T., Masuda, H., Takeda, S., Nakata, M., ... Nakamura, H. (2009). Design and implementation of fine-grain power gating with ground bounce suppression. : Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems (pp. 381-386). [4749703] https://doi.org/10.1109/VLSI.Design.2009.63

Design and implementation of fine-grain power gating with ground bounce suppression. / Usami, Kimiyoshi; Shirai, Toshiaki; Hashida, Tasunori; Masuda, Hiroki; Takeda, Seidai; Nakata, Mitsutaka; Seki, Naomi; Amano, Hideharu; Namiki, Mitaro; Imai, Masashi; Kondo, Masaaki; Nakamura, Hiroshi.

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 381-386 4749703.

研究成果: Conference contribution

Usami, K, Shirai, T, Hashida, T, Masuda, H, Takeda, S, Nakata, M, Seki, N, Amano, H, Namiki, M, Imai, M, Kondo, M & Nakamura, H 2009, Design and implementation of fine-grain power gating with ground bounce suppression. : Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems., 4749703, pp. 381-386, 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems, New Delhi, 09/1/5. https://doi.org/10.1109/VLSI.Design.2009.63
Usami K, Shirai T, Hashida T, Masuda H, Takeda S, Nakata M その他. Design and implementation of fine-grain power gating with ground bounce suppression. : Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. p. 381-386. 4749703 https://doi.org/10.1109/VLSI.Design.2009.63
Usami, Kimiyoshi ; Shirai, Toshiaki ; Hashida, Tasunori ; Masuda, Hiroki ; Takeda, Seidai ; Nakata, Mitsutaka ; Seki, Naomi ; Amano, Hideharu ; Namiki, Mitaro ; Imai, Masashi ; Kondo, Masaaki ; Nakamura, Hiroshi. / Design and implementation of fine-grain power gating with ground bounce suppression. Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems. 2009. pp. 381-386
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