Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano

研究成果: Conference contribution

1 引用 (Scopus)

抄録

Standard Cell based Memory (SCM) is drawing attention as a technique to use the standard digital design flow to realize embedded memory macros. One of the strong points of SCM is that it correctly operates at such low voltage that SRAM macros provided by vendors usually do not work. This paper describes a design of energy-efficient SCM using Silicon-on-Thin-BOX (SOTB). We present automatic layout methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Results from simulations and chip measurements have demonstrated effectiveness of this approach.

元の言語English
ホスト出版物のタイトルProceedings - International SoC Design Conference 2017, ISOCC 2017
出版者Institute of Electrical and Electronics Engineers Inc.
ページ148-149
ページ数2
ISBN(電子版)9781538622858
DOI
出版物ステータスPublished - 2018 5 29
イベント14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of
継続期間: 2017 11 52017 11 8

Other

Other14th International SoC Design Conference, ISOCC 2017
Korea, Republic of
Seoul
期間17/11/517/11/8

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Data storage equipment
Macros
Computer peripheral equipment
Flip flop circuits
Static random access storage
Silicon
Bias voltage
Voltage scaling
Networks (circuits)
Electric potential

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

これを引用

Yoshida, Y., Usami, K., & Amano, H. (2018). Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. : Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 148-149). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368840

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. / Yoshida, Yusuke; Usami, Kimiyoshi; Amano, Hideharu.

Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 148-149.

研究成果: Conference contribution

Yoshida, Y, Usami, K & Amano, H 2018, Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. : Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., pp. 148-149, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368840
Yoshida Y, Usami K, Amano H. Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. : Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 148-149 https://doi.org/10.1109/ISOCC.2017.8368840
Yoshida, Yusuke ; Usami, Kimiyoshi ; Amano, Hideharu. / Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 148-149
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