The design philosophy for a time-division teletext equalizer, that is compact and suitable for circuit integration is proposed. Except for a 17-kilobit RAM for an input waveform memory and a 4. 2-kbit ROM for control signals, the equalizer can be realized with 3000 logic gates. Input offset causes tap weight offset and then causes output bending at the beginning and the end of the teletext signal packet. This phenomenon, which is characteristic of a teletext equalizer, must be prevented. An analysis shows that input level-shift is more effective than output level-shift, and that an input level-shift circuit alone suffices. A breadboard model of a teletext equalizer has been constructed. This equalizer has shown excellent performance.
|ホスト出版物のタイトル||Unknown Host Publication Title|
|出版物ステータス||Published - 1984|
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