Dynamic sleep control for finite-state-machines to reduce active leakage power

Engineering & Materials Science

• Finite automata 73%
• Sleep 71%
• Transistors 57%
• Degradation 31%
• Combinatorial circuits 28%
• Logic gates 26%
• Flip flop circuits 26%
• Logic circuits 25%
• Testing 23%
• Clocks 19%
• Throughput 15%
• Hot Temperature 10%
• Temperature 9%

Mathematics

• Sleep 100%
• Finite State Machine 89%
• Leakage 88%
• Burn-in 29%
• Degradation 23%
• Logic 15%
• Testing 13%
• Throughput 12%
• State Transition 12%
• Flip 10%
• Simulation 6%
• Performance 5%