Energy-efficient standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)

Yusuke Yoshida, Kimiyoshi Usami

研究成果: Article

抜粋

This paper describes a design of energy-efficient Standard Cell Memory (SCM) using Silicon-on-Thin-BOX (SOTB). We present automatic place and routing (P&R) methodology for optimal body-bias separation (BBS) for SCM, which enables to apply different body bias voltages to latches and to other peripheral circuits within SCM. Capability of SOTB to effectively reduce leakage by body biasing is fully exploited in BBS. Simulation results demonstrated that our approach allows us to design SCM with 40% smaller energy dissipation at the energy minimum voltage as compared to the conventional design flow. For the process and temperature variations, Adaptive Body Bias (ABB) for SCM with our BBS provided 70% smaller leakage energy than ABB for the conventional SCM, while achieving the same clock frequency.

元の言語English
ページ(範囲)2785-2796
ページ数12
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E100A
発行部数12
DOI
出版物ステータスPublished - 2017 12 1

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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