Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.

本文言語English
ホスト出版物のタイトルProceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
出版社Institute of Electrical and Electronics Engineers Inc.
ページ91-98
ページ数8
ISBN(電子版)9781538674031
DOI
出版ステータスPublished - 2018 11 15
イベント7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018 - Hakodate, Japan
継続期間: 2018 8 282018 8 31

出版物シリーズ

名前Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018

Other

Other7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
CountryJapan
CityHakodate
Period18/8/2818/8/31

ASJC Scopus subject areas

  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality

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