Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures

Haruya Fujita, Hiroki Takatani, Yosuke Tanaka, Shohei Kawaguchi, Masaomi Sato, Toshio Sudo

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level. So chip level counter-measure is even more important to reduce EMI as an excitation source of noise. In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip. One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors. Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design. It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region.

本文言語English
ホスト出版物のタイトルEMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits
出版社IEEE Computer Society
ページ142-146
ページ数5
ISBN(印刷版)9781479923151
DOI
出版ステータスPublished - 2013
イベント9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013 - Nara, Japan
継続期間: 2013 12 152013 12 18

出版物シリーズ

名前EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits

Conference

Conference9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013
国/地域Japan
CityNara
Period13/12/1513/12/18

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学

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