Automatic road lane detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick control of the vehicle following lanes, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road lane detection by using a small-type parallel image processor. Here, computational time is reduced by developing a lane detection algorithm regarding the parallel processing concept of that hardware. According to the experiments, we could limit average computational time for 20 milliseconds with a good lane detection performance.