Fine-grained power control using a multi-voltage variable pipeline router

Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano

研究成果: Paper

4 被引用数 (Scopus)

抄録

We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same operating frequency, and thus there is noneed to synchronize neighboring routers working at differentfrequencies. The proposed power management policy makes thesupply voltage of each input and output channel low wheneverthe channel is idle. A MVFG-VP router is designed by using a65nm process and evaluated using a full-system CMP simulator. Evaluation results show that the power consumption is reducedby 33.6% while the performance overhead is only 4.4%compared to a conventional router. In addition, the fine-grainpower management approach is compared to a coarse-grainpower management (for a Multi-Vdd Coarse-Grained VariablePipeline router: MVCG-VP router) that simply controls thesupply voltage of a whole router. The results show that finegrainand less energy overhead approach reduces the powerconsumption by 16.6% compared to the coarse-grain approachwith the same application performance.

本文言語English
ページ59-66
ページ数8
DOI
出版ステータスPublished - 2012 12 1
イベント2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012 - Aizu-Wakamatsu, Fukushima, Japan
継続期間: 2012 9 202012 9 22

Conference

Conference2012 IEEE 6th International Symposium on Embedded Multi-Core Systems on Chips, MCSoC 2012
CountryJapan
CityAizu-Wakamatsu, Fukushima
Period12/9/2012/9/22

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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