A systematic method to verify designs within a product line based on formal verification techniques is presented. Model checking techniques to design verification, which is a formal verification technique in which the target system is described as a finite state model and provide some logical properties, was applied. Test scenarios were utilize for the design verification because it is a typical method for defining verification items. The application of the design verification was examine in the context of product line development for the verification by reuse. The variation points in the verification model were defined, a technique using UML has been been proposed that denotes variation points and variants by attaching certain stereotypes, to reuse the model in product line development. This formal verification techniques is one of the promising techniques to develop reliable embedded software.
ASJC Scopus subject areas
- コンピュータ サイエンス（全般）