A GaAs buffering circuit LSI for ultra-fast data processing systems has been developed. The LSI with CML compatible interface and +1.5/-3.3-V power supply voltage has successfully achieved 2-ns data cycle time with 4.8-W chip power dissipation. The circuit was designed to accommodate the basic variations in FET parameters over the operating temperature range. Refractory metal gate lightly-doped drain (LDD) MESFET technology was employed. The gate length is 1.0 μm. WSi-W bilayer metallization system was used to reduce the gate resistance.
|出版ステータス||Published - 1988 12月 1|
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