A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Ω to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. The total thermal resistance from the chip to the ambient medium was approximately 3°C/W. A 3-Gb/s data transfer rate (32 b × 100 MHz) can be realized by four stacked modules of 48 GaAs BLs.
|ジャーナル||Proceedings - Electronic Components and Technology Conference|
|出版ステータス||Published - 1990 12 1|
|イベント||1990 Proceedings of the 40th Electronic Components and Technology Conference - Las Vegas, NV, USA|
継続期間: 1990 5 20 → 1990 5 23
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