Geyser-2: The second prototype CPU with fine-grained run-time power gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

研究成果: Conference contribution

10 引用 (Scopus)
元の言語English
ホスト出版物のタイトル2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
ページ87-88
ページ数2
DOI
出版物ステータスPublished - 2011 3 28
イベント2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
継続期間: 2011 1 252011 1 28

出版物シリーズ

名前Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Japan
Yokohama
期間11/1/2511/1/28

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

これを引用

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H., & Kondo, M. (2011). Geyser-2: The second prototype CPU with fine-grained run-time power gating. : 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 (pp. 87-88). [5722310] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2011.5722310