Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

L. Zhao, D. Ikebuchi, Y. Saito, M. Kamata, N. Seki, Y. Kojima, H. Amano, S. Koyama, T. Hashida, Y. Umahashi, D. Masuda, K. Usami, K. Kimura, M. Namiki, S. Takeda, H. Nakamura, M. Kondo

研究成果: Article

10 引用 (Scopus)
元の言語English
ページ(範囲)87-88
ジャーナル16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011
出版物ステータスPublished - 2011 1 26

これを引用

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H., & Kondo, M. (2011). Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating. 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011, 87-88.