Hierarchical symbolic design methodology for large-scale data paths

Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori

研究成果: Article

抄録

A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.

元の言語English
ページ(範囲)381-385
ページ数5
ジャーナルIEEE Journal of Solid-State Circuits
26
発行部数3
DOI
出版物ステータスPublished - 1991 3
外部発表Yes

Fingerprint

Turnaround time
Adders
Microprocessor chips
Masks
Transistors
Compaction
Productivity
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Hierarchical symbolic design methodology for large-scale data paths. / Usami, Kimiyoshi; Sugeno, Yukio; Matsumoto, Nobu; Mori, Shojiro.

:: IEEE Journal of Solid-State Circuits, 巻 26, 番号 3, 03.1991, p. 381-385.

研究成果: Article

Usami, Kimiyoshi ; Sugeno, Yukio ; Matsumoto, Nobu ; Mori, Shojiro. / Hierarchical symbolic design methodology for large-scale data paths. :: IEEE Journal of Solid-State Circuits. 1991 ; 巻 26, 番号 3. pp. 381-385.
@article{397b409b97154c4bb6e5c2cc62913b35,
title = "Hierarchical symbolic design methodology for large-scale data paths",
abstract = "A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.",
author = "Kimiyoshi Usami and Yukio Sugeno and Nobu Matsumoto and Shojiro Mori",
year = "1991",
month = "3",
doi = "10.1109/4.75017",
language = "English",
volume = "26",
pages = "381--385",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - Hierarchical symbolic design methodology for large-scale data paths

AU - Usami, Kimiyoshi

AU - Sugeno, Yukio

AU - Matsumoto, Nobu

AU - Mori, Shojiro

PY - 1991/3

Y1 - 1991/3

N2 - A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.

AB - A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.

UR - http://www.scopus.com/inward/record.url?scp=0026119963&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026119963&partnerID=8YFLogxK

U2 - 10.1109/4.75017

DO - 10.1109/4.75017

M3 - Article

AN - SCOPUS:0026119963

VL - 26

SP - 381

EP - 385

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 3

ER -