抄録
A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.
| 元の言語 | English |
|---|---|
| ページ（範囲） | 381-385 |
| ページ数 | 5 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | 26 |
| 発行部数 | 3 |
| DOI | |
| 出版物ステータス | Published - 1991 3 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
これを引用
Hierarchical symbolic design methodology for large-scale data paths. / Usami, Kimiyoshi; Sugeno, Yukio; Matsumoto, Nobu; Mori, Shojiro.
：: IEEE Journal of Solid-State Circuits, 巻 26, 番号 3, 03.1991, p. 381-385.研究成果: Article
}
TY - JOUR
T1 - Hierarchical symbolic design methodology for large-scale data paths
AU - Usami, Kimiyoshi
AU - Sugeno, Yukio
AU - Matsumoto, Nobu
AU - Mori, Shojiro
PY - 1991/3
Y1 - 1991/3
N2 - A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.
AB - A symbolic layout methodology for large-scale data paths is proposed. A gate-level symbolic expression, the logic transformation diagram, is adopted as a layout input. A mask layout is automatically generated from the symbolic expression. A hierarchical design method is used in combination with a bit-slice regular structure and a performance-determining irregular structure. A 1-b field of the bit-slice structure is designed symbolically and then compacted, and finally the entire data path is generated. Performance-determining irregular macrocells, such as adders with carry-look-ahead (CLA) circuits, are handcrafted independently and combined with the entire data path at the final step. To achieve high density and high performance, effort is focused on optimizing the layout of the 1-b field. Iteration of the editing and compaction loop can be executed in a short turnaround time (TAT). By the proposed methodology, a data path containing 21K transistors in a 32-b microprocessor has been successfully produced. Design productivity has been increased tenfold, achieving a layout density equivalent to that of the handcrafted design.
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UR - http://www.scopus.com/inward/citedby.url?scp=0026119963&partnerID=8YFLogxK
U2 - 10.1109/4.75017
DO - 10.1109/4.75017
M3 - Article
AN - SCOPUS:0026119963
VL - 26
SP - 381
EP - 385
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 3
ER -