High-efficiency enhancement-mode power heterojunction FET with Buried p+-GaAs gate structure for low-voltage-operated mobile applications

Yasunori Bito, Yoshiaki Yamakawa, Shinichi Tanaka, Naotaka Iwata

研究成果: Article

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This letter describes a successfully developed enhancement-mode double-doped AlGaAs/InGaAs/AlGaAs heterojunction FET with a buried p+-n junction gate structure for low-voltage-operated mobile applications. The buried p+-GaAs gate structure effectively reduced on-resistance (Ron) and suppressed drain-current frequency dispersion for the device with high positive threshold voltage, resulting in high-efficiency characteristics under low-voltage operation. The fabricated p+-gate HJFET exhibited a low Ron of 1.4 Ω · mm with a threshold voltage of +0.4 V. Negligible frequency dispersion characteristics were obtained through pulsed current-voltage measurements for the device. Under a single 2.7-V operation, a 19.8-mm gate width device exhibited a power added efficiency of 51.9% with 26.8-dBm output power and a -40.1-dBc adjacent channel power ratio using a 1.95-GHz wideband code-division multiple-access signal.

元の言語English
ページ(範囲)636-639
ページ数4
ジャーナルIEEE Electron Device Letters
27
発行部数8
DOI
出版物ステータスPublished - 2006 8 1
外部発表Yes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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