High-Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing Sst (Scarce State Transition) Scheme

S. Kubota, K. Ohtani, S. Kato

研究成果: Article査読

17 被引用数 (Scopus)

抄録

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pε performance (4-2 dB net coding gain at Pε = 1 x 10-6), drastic reduction of power consumption and number of gates with low development costs.

本文言語English
ページ(範囲)491-493
ページ数3
ジャーナルElectronics Letters
22
9
DOI
出版ステータスPublished - 1986 1 1
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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