抜粋
This paper describes a new GaAs static flip-flop, called TD-FF (Tri-state Driver Flip-Flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value ever reported for D-FFs (Delay-type Flip-Flops). The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | NEC Research and Development |
| ページ | 157-164 |
| ページ数 | 8 |
| 巻 | 36 |
| エディション | 1 |
| 出版物ステータス | Published - 1995 1 1 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
フィンガープリント High-speed low-power tri-state driver flip-flop for sub-1 V supply voltage GaAs heterojunction FET LSIs' の研究トピックを掘り下げます。これらはともに一意のフィンガープリントを構成します。
これを引用
Maeda, T., Numata, K., Tokushima, M., Ishikawa, M., Fukaishi, M., Hida, H., & Ohno, Y. (1995). High-speed low-power tri-state driver flip-flop for sub-1 V supply voltage GaAs heterojunction FET LSIs. ： NEC Research and Development (1 版, 巻 36, pp. 157-164)