High-speed low-power tri-state driver flip-flop for sub-1 V supply voltage GaAs heterojunction FET LSIs

Tadashi Maeda, Keiichi Numata, Masatoshi Tokushima, Masaoki Ishikawa, Muneo Fukaishi, Hikaru Hida, Yasuo Ohno

研究成果: Chapter

抄録

This paper describes a new GaAs static flip-flop, called TD-FF (Tri-state Driver Flip-Flop), for ultra-low supply voltage GaAs heterojunction FET LSIs. The TD-FF operates at a data rate of 10 Gbps with 18 mW power consumption at 0.8 V supply voltage. The 10 Gbps power consumption is 1/5 of the minimum value ever reported for D-FFs (Delay-type Flip-Flops). The authors also demonstrate a 1/8 static frequency divider IC using the TD-FF configuration. This IC operates up to 10 GHz with 38 mW at 0.8 V supply voltage.

本文言語English
ホスト出版物のタイトルNEC Research and Development
ページ157-164
ページ数8
36
1
出版ステータスPublished - 1995 1月 1
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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