抄録
A high transconductance of 602 mS/mm has been obtained in 0. 3 micrometer-long gate GaAs MESFETs using a combined sidewall-assisted self-alignment technology and WSi//x gate n** plus selective ion implantation technology. The gate orientation effect for the fabricated FET is enhanced by lateral diffusion of implanted n** plus impurities to the channel region. 25-stage ring oscillators with an E/D DCFL configuration were also fabricated using 0. 7 micrometer-long gate FETs. The minimum propagation delay time of 16 ps/gate was observed.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | Conference on Solid State Devices and Materials |
| 出版場所 | Tokyo, Jpn |
| 出版者 | Japan Soc of Applied Physics |
| ページ | 405-408 |
| ページ数 | 4 |
| ISBN（印刷物） | 4930813107 |
| 出版物ステータス | Published - 1985 |
| 外部発表 | Yes |
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ASJC Scopus subject areas
- Engineering(all)
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HIGH TRANSCONDUCTANCE GaAs MESFETs FABRICATED USING SIDEWALL-ASSISTED SELF-ALIGNMENT TECHNOLOGY (SWAT). / Ueno, K.; Furutsuka, T.; Kanamori, M.; Higashisaka, A.
Conference on Solid State Devices and Materials. Tokyo, Jpn : Japan Soc of Applied Physics, 1985. p. 405-408.研究成果: Conference contribution
}
TY - GEN
T1 - HIGH TRANSCONDUCTANCE GaAs MESFETs FABRICATED USING SIDEWALL-ASSISTED SELF-ALIGNMENT TECHNOLOGY (SWAT).
AU - Ueno, K.
AU - Furutsuka, T.
AU - Kanamori, M.
AU - Higashisaka, A.
PY - 1985
Y1 - 1985
N2 - A high transconductance of 602 mS/mm has been obtained in 0. 3 micrometer-long gate GaAs MESFETs using a combined sidewall-assisted self-alignment technology and WSi//x gate n** plus selective ion implantation technology. The gate orientation effect for the fabricated FET is enhanced by lateral diffusion of implanted n** plus impurities to the channel region. 25-stage ring oscillators with an E/D DCFL configuration were also fabricated using 0. 7 micrometer-long gate FETs. The minimum propagation delay time of 16 ps/gate was observed.
AB - A high transconductance of 602 mS/mm has been obtained in 0. 3 micrometer-long gate GaAs MESFETs using a combined sidewall-assisted self-alignment technology and WSi//x gate n** plus selective ion implantation technology. The gate orientation effect for the fabricated FET is enhanced by lateral diffusion of implanted n** plus impurities to the channel region. 25-stage ring oscillators with an E/D DCFL configuration were also fabricated using 0. 7 micrometer-long gate FETs. The minimum propagation delay time of 16 ps/gate was observed.
UR - http://www.scopus.com/inward/record.url?scp=0022246983&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0022246983&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0022246983
SN - 4930813107
SP - 405
EP - 408
BT - Conference on Solid State Devices and Materials
PB - Japan Soc of Applied Physics
CY - Tokyo, Jpn
ER -