Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond

T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E. Apen, K. Chattopadhyay, B. Van Schravendijk, N. Oda, M. Sekine

研究成果: Conference contribution

20 被引用数 (Scopus)

抄録

A highly reliable interface using a self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) has been developed for 65mn node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure in addition, 39× via electro-migration (EM) improvement and 1.5× better TZDM were obtained in companson to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TBM-EELS. According to these analyses, the mechanism for performance enhancement is proposed.

本文言語English
ホスト出版物のタイトル2006 International Interconnect Technology Conference, IITC
ページ125-127
ページ数3
DOI
出版ステータスPublished - 2006
外部発表はい
イベント2006 International Interconnect Technology Conference, IITC - Burlingame, CA, United States
継続期間: 2006 6 52006 6 7

出版物シリーズ

名前2006 International Interconnect Technology Conference, IITC

Conference

Conference2006 International Interconnect Technology Conference, IITC
国/地域United States
CityBurlingame, CA
Period06/6/506/6/7

ASJC Scopus subject areas

  • 制御およびシステム工学
  • 電子工学および電気工学

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