Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Toshiaki Shirai, Kimiyoshi Usami

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

Increase in leakage power and Vth variation is a critical concern in leading-edge CMOS technology. Traditional dual Vth design with the worst corner model becomes difficult to achieve for low leakage because delay variation of high Vth cell is increased significantly by Vth variation. In this paper, we demonstrated that a power gated cell is more tolerant in delay variation than high Vth cell in 45nm technology. We propose hybrid design technique to use power gated cells in the dual Vth circuit to reduce standby leakage without causing performance degradation. Also, we developed an optimization methodology based on simulated annealing. The proposed technique was applied to ISCAS'85 benchmark circuits. Standby leakage power was reduced by 44% on average over the conventional dual Vth design.

元の言語English
ホスト出版物のタイトル2008 International SoC Design Conference, ISOCC 2008
ページI310-I313
DOI
出版物ステータスPublished - 2008 12 1
イベント2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
継続期間: 2008 11 242008 11 25

出版物シリーズ

名前2008 International SoC Design Conference, ISOCC 2008
1

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
Korea, Republic of
Busan
期間08/11/2408/11/25

    フィンガープリント

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

これを引用

Shirai, T., & Usami, K. (2008). Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations. : 2008 International SoC Design Conference, ISOCC 2008 (pp. I310-I313). [4815634] (2008 International SoC Design Conference, ISOCC 2008; 巻数 1). https://doi.org/10.1109/SOCDC.2008.4815634