Improved delayering method for soi wafer processing

Handie Ahmataku, Shahrol Mohamaddan, Mahshuri Yusuf, Aidil Azli Alias, Kuryati Kipli, Norhayati Soin

研究成果: Conference contribution

抄録

The benefits of Silicon on Insulator (SOI) technology are to reduce parasitic device capacitance, improving performance as well as smaller build area. Current delayering method to reveal polysilicon using 49% Hydrofluoric (HF) concentration is not suitable for SOI wafer. Furthermore, the method cannot remove small, thin and dense gate poly such as in Static Random Access Memory (SRAM) cells. The implication of the current method will cause Top Silicon to be damaged. A parallel lapping is used to improve surface flatness while exposing the polysilicon layer. Subsequently, Poly-etchant is employed to etch the exposed polysilicon and remaining the oxides. An optimum HF's concentration and etching time are crucial in order to etch the remaining oxides while protect Top Silicon from damage during SOI delayering process. The idea is to halt the oxide etching somewhere in Deep Trench Isolation (DTI) without delaminating Top Silicon on Buried Oxide (BOX). In addition to this process, Interlayer Dielectric (ILD) oxide, Gate Oxide (GOX) and polysilicon layer can be removed completely. Hence, 20% HF and 10 minutes etching time (HFt) followed by supersonic cleaning is a recommended combination for a complete removal of remaining layers on silicon surface, such as metals, polysilicon, nitride, and oxides. A clean exposed silicon substrate is vital to allow wet etchant solution to be carried out successfully to reveal silicon defects. Improved delayering method of Parallel Lapping → Poly-Etchant → Diluted and Time Controlled Hydrofluoric Acid Etching is capable to remove thin and dense polysilicon precisely without damaging the Top Silicon made it suitable for SOI technology.

本文言語English
ホスト出版物のタイトルIPFA 2018 - 25th International Symposium on the Physical and Failure Analysis of Integrated Circuits
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(印刷版)9781538649299
DOI
出版ステータスPublished - 2018 8 30
外部発表はい
イベント25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018 - Singapore, Singapore
継続期間: 2018 7 162018 7 19

出版物シリーズ

名前Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
2018-July

Conference

Conference25th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2018
国/地域Singapore
CitySingapore
Period18/7/1618/7/19

ASJC Scopus subject areas

  • 電子工学および電気工学

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