Improvement of simultaneous switching noise simulation considering on-chip capacitance

Kunio Ota, Kazuhisa Matsuge, Yo Takahashi, Toshio Sudo

研究成果: Conference contribution

抄録

Simultaneous switching noise (SSN) causes signal degradation to the high-speed interfaces among CMOS VLSIs. To achieve SSN simulation with a high accuracy, accurate models for chips, packages and printed circuit boards (PCBs) are required. However, such accurate simulation models are not currently available, since chip vendors do not release the value of on-chip capacitance and the detailed package model with mutual inductances. This paper presents our approach for establishing an accurate model without detailed information on the chip and package. The three key points of our approach are the measurement of on-chip capacitance using a vector network analyzer (VNA), the measurement of quad flat package (QFP) dimensions using X-ray photographs, and the application of 3-D electromagnetic field solver to extract a detailed equivalent circuit model for the package from a geometrical structure. The simulated SSN time-domain waveforms showed an extremely good agreement with the measured results.

本文言語English
ホスト出版物のタイトルIEEE International Symposium on Electromagnetic Compatibility, EMC 2010 - Final Program
ページ284-288
ページ数5
DOI
出版ステータスPublished - 2010 12 1
イベント2010 IEEE International Symposium on Electromagnetic Compatibility, EMC 2010 - Fort Lauderdale, FL, United States
継続期間: 2010 7 252010 7 30

出版物シリーズ

名前IEEE International Symposium on Electromagnetic Compatibility
ISSN(印刷版)1077-4076

Conference

Conference2010 IEEE International Symposium on Electromagnetic Compatibility, EMC 2010
国/地域United States
CityFort Lauderdale, FL
Period10/7/2510/7/30

ASJC Scopus subject areas

  • 凝縮系物理学
  • 電子工学および電気工学

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