Influence of anti-resonance peak in power supply network on power and signal integrity

Toma Yamaguchi, Yusuke Hatogai, Toshio Sudo

研究成果: Conference contribution

抄録

Reduction of PDN impedance is necessary to prevent false logic operation of the CMOS LSIs. Constant target impedance with frequency is used as a simple method to define PDN impedance of the system. However, this conventional target impedance did not change with frequency, and was not applied to the high frequency range where PDN impedance exceeds the constant value of target impedance. Therefore, newly frequency dependent target impedance has been derived and applied to the DDR3 memory system. Co-simulation model has been established to estimate power Integrity (PI) and signal Integrity (SI) at the same time. The switching current flowing from the chip was connected to the whole PDN model, and power supply noise and eyes diagram were simulated. The new target impedance has been proved to be reasonable for maintaining the power supply noise and the eye diagrams.

本文言語English
ホスト出版物のタイトルProceedings of the 2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
ページ224-228
ページ数5
出版ステータスPublished - 2013 12 24
イベント2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013 - Brugge, Belgium
継続期間: 2013 9 22013 9 6

出版物シリーズ

名前IEEE International Symposium on Electromagnetic Compatibility
ISSN(印刷版)1077-4076
ISSN(電子版)2158-1118

Conference

Conference2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
CountryBelgium
CityBrugge
Period13/9/213/9/6

ASJC Scopus subject areas

  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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