An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.
|出版ステータス||Published - 1997 12月 1|
|イベント||Proceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA|
継続期間: 1997 10月 12 → 1997 10月 15
|Other||Proceedings of the 1997 19th Annual GaAs IC Symposium|
|City||Anaheim, CA, USA|
|Period||97/10/12 → 97/10/15|
ASJC Scopus subject areas