Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

Nobuhide Yoshida; Masahiro Fujii; Takao Atsumo; Keiichi Numata; Shuji Asai; Michihisa Kohno; Hirokazu Oikawa; Hiroaki Tsutsui; Tadeshi Maeda

Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

Nobuhide Yoshida, Masahiro Fujii, Takao Atsumo, Keiichi Numata, Shuji Asai, Michihisa Kohno, Hirokazu Oikawa, Hiroaki Tsutsui, Tadeshi Maeda

研究成果 › 査読

8 被引用数 (Scopus)

抄録

An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

本文言語	English
ページ	113-116
ページ数	4
出版ステータス	Published - 1997 12 1
外部発表	はい
イベント	Proceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA 継続期間: 1997 10 12 → 1997 10 15

Other

Other	Proceedings of the 1997 19th Annual GaAs IC Symposium
City	Anaheim, CA, USA
Period	97/10/12 → 97/10/15

ASJC Scopus subject areas

工学（全般）

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引用スタイル

@conference{04e70071ce534e868541092fc3317dd4,

title = "Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer",

abstract = "An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.",

author = "Nobuhide Yoshida and Masahiro Fujii and Takao Atsumo and Keiichi Numata and Shuji Asai and Michihisa Kohno and Hirokazu Oikawa and Hiroaki Tsutsui and Tadeshi Maeda",

year = "1997",

month = dec,

day = "1",

language = "English",

pages = "113--116",

note = "Proceedings of the 1997 19th Annual GaAs IC Symposium ; Conference date: 12-10-1997 Through 15-10-1997",

}

TY - CONF

T1 - Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

AU - Yoshida, Nobuhide

AU - Fujii, Masahiro

AU - Atsumo, Takao

AU - Numata, Keiichi

AU - Asai, Shuji

AU - Kohno, Michihisa

AU - Oikawa, Hirokazu

AU - Tsutsui, Hiroaki

AU - Maeda, Tadeshi

PY - 1997/12/1

Y1 - 1997/12/1

N2 - An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

AB - An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

UR - http://www.scopus.com/inward/record.url?scp=0031372243&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0031372243&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0031372243

SP - 113

EP - 116

T2 - Proceedings of the 1997 19th Annual GaAs IC Symposium

Y2 - 12 October 1997 through 15 October 1997

ER -

Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

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